[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-entities)

<br>

# Entity - data_seq_compute

## Summary

| Name | Location | Description |
| --- | --- | --- |
|data_seq_compute|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#32">data_seq_compute.vhd#32</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_data_seq_compute | <linty-anchor href="/src/module_data_link/data_link.vhd#1138">data_link.vhd#1138</linty-anchor> |  | [<img title="View Instantiation Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_22/instantiation_1.md) |


## Generics

Count: 0

## Ports

Count: 16

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#34">CLK</linty-anchor>|in|std_logic|Clock generated by GTY IP|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#36">LINK_RESET_DLRE</linty-anchor>|in|std_logic|Link Reset command|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#38">LANE_ACTIVE_PPL</linty-anchor>|in|std_logic|Lane Active flag for the DATA Link Layer|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#40">NEW_WORD_DENC</linty-anchor>|in|std_logic|New word flag associated with DATA_DENC|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#41">DATA_DENC</linty-anchor>|in|std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )|Data parallel from data_encapsulation|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#42">VALID_K_CHARAC_DENC</linty-anchor>|in|std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )|K charachter valid in the 32-bit DATA_DENC vector|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#43">TYPE_FRAME_DENC</linty-anchor>|in|std_logic_vector ( C_TYPE_FRAME_LENGTH - 1 downto 0 )|Type of the frame associated with DATA_DENC|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#44">END_FRAME_DENC</linty-anchor>|in|std_logic|End frame/control word associated with DATA_DENC|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#45">SEQ_NUM_ACK_DENC</linty-anchor>|in|std_logic_vector ( 7 downto 0 )|SEQ_NUM ACK value|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#46">TRANS_POL_FLG_DENC</linty-anchor>|in|std_logic|Transmission polarity flag|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#48">NEW_WORD_DSCOM</linty-anchor>|out|std_logic|New word flag associated with DATA_DSCOM|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#49">DATA_DSCOM</linty-anchor>|out|std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )|Data parallel to data_encapsulation|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#50">VALID_K_CHARAC_DSCOM</linty-anchor>|out|std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )|K charachter valid in the 32-bit DATA_DSCOM vector|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#51">TYPE_FRAME_DSCOM</linty-anchor>|out|std_logic_vector ( C_TYPE_FRAME_LENGTH - 1 downto 0 )|Type of the frame associated with DATA_DSCOM|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#52">END_FRAME_DSCOM</linty-anchor>|out|std_logic|End frame/control word associated with DATA_DSCOM|
|<linty-anchor href="//src/module_data_link/data_seq_compute.vhd#54">SEQ_NUM_DSCOM</linty-anchor>|out|std_logic_vector ( 7 downto 0 )|Current SEQ_NUM value|


<br>

[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-entities)