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# Entity - data_out_buff ## Summary | Name | Location | Description | | --- | --- | --- | |data_out_buff|data_out_buf.vhd#33|| ## Instantiations Count: 8 | Name | Location | Description | Details | | --- | --- | --- | :---: | | gen_data_out_buff(0)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_1.md) | | gen_data_out_buff(1)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_2.md) | | gen_data_out_buff(2)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_3.md) | | gen_data_out_buff(3)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_4.md) | | gen_data_out_buff(4)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_5.md) | | gen_data_out_buff(5)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_6.md) | | gen_data_out_buff(6)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_7.md) | | gen_data_out_buff(7)\.inst_data_out_buff | data_link.vhd#1041 | | [View Instantiation Details](module_20/instantiation_8.md) | ## Generics Count: 0 ## Ports Count: 22 | Name | Mode | Type | Description | | --- | --- | --- | --- | |RST_N|in|std_logic|Global reset (Active-low)| |CLK|in|std_logic|Global Clock| |LANE_ACTIVE_ST_PPL|in|std_logic|Lane Active state flag| |LINK_RESET_DLRE|in|std_logic|Link Reset command| |S_AXIS_ARSTN_NW|in|std_logic|Active-low asynchronous reset signal for the AXI-Stream i| |S_AXIS_ACLK_NW|in|std_logic|Clock signal for the AXI-Stream interface| |S_AXIS_TREADY_DL|out|std_logic|Ready signal from the slave indicating it can accept data| |S_AXIS_TDATA_NW|in|std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )|Data bus carrying the actual payload| |S_AXIS_TUSER_NW|in|std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )|User-defined sideband information (optional)| |S_AXIS_TLAST_NW|in|std_logic|Signal indicating the last transfer in a packet| |S_AXIS_TVALID_NW|in|std_logic|Valid signal indicating that the data on TDATA is valid| |VC_READY_DOBUF|out|std_logic|Virtual Channel ready flag| |DATA_DOBUF|out|std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )|Data parallel to data_mac| |VALID_K_CHARAC_DOBUF|out|std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )|K character valid in the 32-bit DATA_DOBUF vector| |DATA_VALID_DOBUF|out|std_logic|Data valid flag associated with DATA_DOBUF| |END_PACKET_DOBUF|out|std_logic|End packet flag| |VC_RD_EN_DMAC|in|std_logic|Read command from data_mac| |M_VAL_DSCHECK|in|std_logic_vector ( C_M_SIZE - 1 downto 0 )|M value associated with FCT_FAR_END_DSCHECK| |FCT_FAR_END_DSCHECK|in|std_logic|FCT Fare-end received flag| |FCT_CC_OVF_DOBUF|out|std_logic|FCT credit counter overflow flag| |CREDIT_VC_DOBUF|out|std_logic|Has credit flag (crdit counter > 0)| |VC_CONT_MODE_MIB|in|std_logic|Continuous mode command|
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