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# Entity - data_link

## Summary

| Name | Location | Description |
| --- | --- | --- |
|data_link|<linty-anchor href="//src/module_data_link/data_link.vhd#31">data_link.vhd#31</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_data_link | <linty-anchor href="/src/ip_spacefibre_light_top/spacefibre_light_top.vhd#567">spacefibre_light_top.vhd#567</linty-anchor> |  | [<img title="View Instantiation Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_16/instantiation_1.md) |


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//src/module_data_link/data_link.vhd#33">G_VC_NUM</linty-anchor>|integer|8|Number of virtual channel|
## Ports

Count: 69

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//src/module_data_link/data_link.vhd#36">RST_N</linty-anchor>|in|std_logic|global reset|
|<linty-anchor href="//src/module_data_link/data_link.vhd#37">CLK</linty-anchor>|in|std_logic|Clock generated by GTY IP|
|<linty-anchor href="//src/module_data_link/data_link.vhd#39">AXIS_ARSTN_TX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Active-low asynchronous reset signals for each virtual channel (VC) in the TX path|
|<linty-anchor href="//src/module_data_link/data_link.vhd#40">AXIS_ACLK_TX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Clock signals for each VC in the TX path|
|<linty-anchor href="//src/module_data_link/data_link.vhd#41">AXIS_TREADY_TX_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that the data link layer is ready to accept data on each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#42">AXIS_TDATA_TX_NW</linty-anchor>|in|vc_data_array ( G_VC_NUM downto 0 )|Data signals from the network layer to the data link layer for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#43">AXIS_TUSER_TX_NW</linty-anchor>|in|vc_k_array ( G_VC_NUM downto 0 )|Sideband information (e.g., control or metadata) from the network layer to the data link layer for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#44">AXIS_TLAST_TX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Indicates the last transfer in a packet/transaction on each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#45">AXIS_TVALID_TX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that valid data is available on the TX data bus for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#47">AXIS_ARSTN_RX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Active-low asynchronous reset signals for each VC in the RX path|
|<linty-anchor href="//src/module_data_link/data_link.vhd#48">AXIS_ACLK_RX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Clock signals for each VC in the RX path|
|<linty-anchor href="//src/module_data_link/data_link.vhd#49">AXIS_TREADY_RX_NW</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that the network layer is ready to receive data on each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#50">AXIS_TDATA_RX_DL</linty-anchor>|out|vc_data_array ( G_VC_NUM downto 0 )|Data signals from the data link layer to the network layer for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#51">AXIS_TUSER_RX_DL</linty-anchor>|out|vc_k_array ( G_VC_NUM downto 0 )|Sideband information from the data link layer to the network layer for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#52">AXIS_TLAST_RX_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM downto 0 )|Indicates the last transfer in a packet/transaction on each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#53">AXIS_TVALID_RX_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that valid data is available on the RX data bus for each VC|
|<linty-anchor href="//src/module_data_link/data_link.vhd#54">CURRENT_TIME_SLOT_NW</linty-anchor>|in|std_logic_vector ( 7 downto 0 )|Current time slot|
|<linty-anchor href="//src/module_data_link/data_link.vhd#56">DATA_TX_DL</linty-anchor>|out|std_logic_vector ( 31 downto 00 )|Data parallel to be send from Data-Link Layer|
|<linty-anchor href="//src/module_data_link/data_link.vhd#57">CAPABILITY_TX_DL</linty-anchor>|out|std_logic_vector ( 07 downto 00 )|Capability send on TX link in INIT3 control word|
|<linty-anchor href="//src/module_data_link/data_link.vhd#58">NEW_DATA_TX_DL</linty-anchor>|out|std_logic|Flag to write data in FIFO TX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#59">VALID_K_CHARAC_TX_DL</linty-anchor>|out|std_logic_vector ( 03 downto 00 )|K charachter valid in the 32-bit DATA_TX_DL vector|
|<linty-anchor href="//src/module_data_link/data_link.vhd#60">FIFO_TX_FULL_PPL</linty-anchor>|in|std_logic|Flag full of the FIFO TX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#62">FIFO_RX_RD_EN_DL</linty-anchor>|out|std_logic|Flag to read data in FIFO RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#63">DATA_RX_PPL</linty-anchor>|in|std_logic_vector ( 31 downto 00 )|Data parallel to be received to Data-Link Layer|
|<linty-anchor href="//src/module_data_link/data_link.vhd#64">FIFO_RX_EMPTY_PPL</linty-anchor>|in|std_logic|Flag EMPTY of the FIFO RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#65">FIFO_RX_DATA_VALID_PPL</linty-anchor>|in|std_logic|Flag DATA_VALID of the FIFO RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#66">VALID_K_CHARAC_RX_PPL</linty-anchor>|in|std_logic_vector ( 03 downto 00 )|K charachter valid in the 32-bit DATA_TR_PPL vector|
|<linty-anchor href="//src/module_data_link/data_link.vhd#67">FAR_END_CAPA_PPL</linty-anchor>|in|std_logic_vector ( 07 downto 00 )|Capability field receive in INIT3 control word|
|<linty-anchor href="//src/module_data_link/data_link.vhd#68">LANE_ACTIVE_PPL</linty-anchor>|in|std_logic|Lane Active flag for the DATA Link Layer|
|<linty-anchor href="//src/module_data_link/data_link.vhd#69">LANE_RESET_DL</linty-anchor>|out|std_logic|Lane Reset command|
|<linty-anchor href="//src/module_data_link/data_link.vhd#71">INTERFACE_RESET_MIB</linty-anchor>|in|std_logic|Reset the link and all configuration register of the Data Link layer|
|<linty-anchor href="//src/module_data_link/data_link.vhd#72">LINK_RESET_MIB</linty-anchor>|in|std_logic|Reset the link|
|<linty-anchor href="//src/module_data_link/data_link.vhd#73">NACK_RST_EN_MIB</linty-anchor>|in|std_logic|Enable automatic link reset on NACK reception|
|<linty-anchor href="//src/module_data_link/data_link.vhd#74">NACK_RST_MODE_MIB</linty-anchor>|in|std_logic|Up for instant link reset on NACK reception, down for link reset at the end of the current received frame on NACK reception|
|<linty-anchor href="//src/module_data_link/data_link.vhd#75">PAUSE_VC_MIB</linty-anchor>|in|std_logic_vector ( G_VC_NUM downto 0 )|Pause the corresponding virtual channel after the end of current transmission|
|<linty-anchor href="//src/module_data_link/data_link.vhd#76">CONTINUOUS_VC_MIB</linty-anchor>|in|std_logic_vector ( G_VC_NUM - 1 downto 0 )|Enable the corresponding virtual channel continuous mode|
|<linty-anchor href="//src/module_data_link/data_link.vhd#78">SEQ_NUMBER_TX_DL</linty-anchor>|out|std_logic_vector ( 8 - 1 downto 0 )|SEQ_NUMBER in transmission|
|<linty-anchor href="//src/module_data_link/data_link.vhd#79">SEQ_NUMBER_RX_DL</linty-anchor>|out|std_logic_vector ( 8 - 1 downto 0 )|SEQ_NUMBER in reception|
|<linty-anchor href="//src/module_data_link/data_link.vhd#80">CREDIT_VC_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM - 1 downto 0 )|Indicates if each corresponding far-end input buffer has credit|
|<linty-anchor href="//src/module_data_link/data_link.vhd#81">INPUT_BUF_OVF_VC_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM - 1 downto 0 )|Indicates input buffer overflow|
|<linty-anchor href="//src/module_data_link/data_link.vhd#82">FCT_CREDIT_OVERFLOW_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM - 1 downto 0 )|Indicates overflow of each corresponding input buffer|
|<linty-anchor href="//src/module_data_link/data_link.vhd#83">CRC_LONG_ERROR_DL</linty-anchor>|out|std_logic|CRC long error|
|<linty-anchor href="//src/module_data_link/data_link.vhd#84">CRC_SHORT_ERROR_DL</linty-anchor>|out|std_logic|CRC short error|
|<linty-anchor href="//src/module_data_link/data_link.vhd#85">FRAME_ERROR_DL</linty-anchor>|out|std_logic|Frame error|
|<linty-anchor href="//src/module_data_link/data_link.vhd#86">SEQUENCE_ERROR_DL</linty-anchor>|out|std_logic|Sequence error|
|<linty-anchor href="//src/module_data_link/data_link.vhd#87">FAR_END_LINK_RESET_DL</linty-anchor>|out|std_logic|Far-end link reset status|
|<linty-anchor href="//src/module_data_link/data_link.vhd#88">FRAME_FINISHED_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that corresponding channel finished emitting a frame|
|<linty-anchor href="//src/module_data_link/data_link.vhd#89">FRAME_TX_DL</linty-anchor>|out|std_logic_vector ( G_VC_NUM downto 0 )|Indicates that corresponding channel is emitting a frame|
|<linty-anchor href="//src/module_data_link/data_link.vhd#90">DATA_COUNTER_TX_DL</linty-anchor>|out|std_logic_vector ( 6 downto 0 )|Indicate the number of data transmitted in last frame emitted|
|<linty-anchor href="//src/module_data_link/data_link.vhd#91">DATA_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 6 downto 0 )|Indicate the number of data received in last frame received|
|<linty-anchor href="//src/module_data_link/data_link.vhd#92">ACK_COUNTER_TX_DL</linty-anchor>|out|std_logic_vector ( 2 downto 0 )|ACK counter TX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#93">NACK_COUNTER_TX_DL</linty-anchor>|out|std_logic_vector ( 2 downto 0 )|NACK counter TX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#94">FCT_COUNTER_TX_DL</linty-anchor>|out|std_logic_vector ( 3 downto 0 )|FCT counter TX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#95">ACK_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 2 downto 0 )|ACK counter RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#96">NACK_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 2 downto 0 )|NACK counter RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#97">FCT_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 3 downto 0 )|FCT counter RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#98">FULL_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 1 downto 0 )|FULL counter RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#99">RETRY_COUNTER_RX_DL</linty-anchor>|out|std_logic_vector ( 1 downto 0 )|RETRY counter RX|
|<linty-anchor href="//src/module_data_link/data_link.vhd#100">CURRENT_TIME_SLOT_DL</linty-anchor>|out|std_logic_vector ( 7 downto 0 )|Current time slot|
|<linty-anchor href="//src/module_data_link/data_link.vhd#101">RESET_PARAM_DL</linty-anchor>|out|std_logic|Reset configuration parameters control|
|<linty-anchor href="//src/module_data_link/data_link.vhd#102">LINK_RST_ASSERTED_DL</linty-anchor>|out|std_logic|Link has been reseted|
|<linty-anchor href="//src/module_data_link/data_link.vhd#103">NACK_SEQ_NUM_DL</linty-anchor>|out|std_logic_vector ( 7 downto 0 )|NACK Seq_num received|
|<linty-anchor href="//src/module_data_link/data_link.vhd#104">ACK_SEQ_NUM_DL</linty-anchor>|out|std_logic_vector ( 7 downto 0 )|ACK Seq_num received|
|<linty-anchor href="//src/module_data_link/data_link.vhd#105">DATA_PULSE_RX_DL</linty-anchor>|out|std_logic|Data received pulse signal|
|<linty-anchor href="//src/module_data_link/data_link.vhd#106">ACK_PULSE_RX_DL</linty-anchor>|out|std_logic|ACK received pulse signal|
|<linty-anchor href="//src/module_data_link/data_link.vhd#107">NACK_PULSE_RX_DL</linty-anchor>|out|std_logic|NACK received pulse signal|
|<linty-anchor href="//src/module_data_link/data_link.vhd#108">FCT_PULSE_RX_DL</linty-anchor>|out|std_logic|FCT received pulse signal|
|<linty-anchor href="//src/module_data_link/data_link.vhd#109">FULL_PULSE_RX_DL</linty-anchor>|out|std_logic|FULL received pulse signal|
|<linty-anchor href="//src/module_data_link/data_link.vhd#110">RETRY_PULSE_RX_DL</linty-anchor>|out|std_logic|RETRY received pulse signal|


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