# gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising) => inst_reset_sync_clk_from_GTY.reset_gen_rr_n (rising)
|Graph|Origin Clock Domain|Target Clock Domain|Number of CDCs|
|:---:|---|---:|---|
||gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)|inst_reset_sync_clk_from_GTY.reset_gen_rr_n (rising)|1|Graph|
## CDCs
### Summary
|ID|Graph|Origin Signal|Target Signal|Details|
|---:|:---:|---|---|:---:|
|9|Graph|`gen_inst_phy_plus_lane.inst_phy_plus_lane.inst_ppl_64_skip_insertion.WAIT_SEND_DATA_PLSI`|`gen_inst_phy_plus_lane.inst_phy_plus_lane.inst_ppl_64_parallel_loopback.wait_send_data_r`|Details|
### CDC #9
#### Origin Flip-flop
|Graph|Signal|Clock Domain|Flip-flop|
|:---:|---|---|---|
|Graph|Signal: `gen_inst_phy_plus_lane.inst_phy_plus_lane.inst_ppl_64_skip_insertion.WAIT_SEND_DATA_PLSI`
Usage:
- ppl_64_skip_insertion.vhd#152
- ppl_64_skip_insertion.vhd#94
- ppl_64_skip_insertion.vhd#96|gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)|TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_skip_insertion (ppl_64_skip_insertion) > ppl_64_skip_insertion.vhd#83|
#### Target Flip-flop
|Graph|Signal|Clock Domain|Flip-flop|
|:---:|---|---|---|
|Graph|Signal: `gen_inst_phy_plus_lane.inst_phy_plus_lane.inst_ppl_64_parallel_loopback.wait_send_data_r`
Usage:
- ppl_64_parallel_loopback.vhd#76
- ppl_64_parallel_loopback.vhd#77
- ppl_64_parallel_loopback.vhd#78
- ppl_64_parallel_loopback.vhd#80
- ppl_64_parallel_loopback.vhd#81
- ppl_64_parallel_loopback.vhd#82|inst_reset_sync_clk_from_GTY.reset_gen_rr_n (rising)|TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_parallel_loopback (ppl_64_parallel_loopback) > ppl_64_parallel_loopback.vhd#75|